3.6. DWARF Definition

3.6.1. DWARF Release Number

This section defines the Debug With Arbitrary Record Format (DWARF) debugging format for the 64-bit PowerPC processor family. The 64-bit PowerPC ABI does not define a debug format. However, all systems that do implement DWARF shall use the following definitions.

DWARF is a specification developed for symbolic, source-level debugging. The debugging information format does not favor the design of any compiler or debugger. For more information on DWARF, see the documents cited in Chapter 1.

The DWARF definition requires some machine-specific definitions. The register number mapping needs to be specified for the 64-bit PowerPC registers. In addition, the DWARF Version 2 specification requires processor-specific address class codes to be defined.

3.6.2. DWARF Register Number Mapping

This table outlines the register number mapping for the 64-bit PowerPC processor family. Note that for all special purpose registers, the number is simply 100 plus the SPR register number, as defined in the 64-bit PowerPC Architecture. Registers with an asterisk before their name are MPC601 chip-specific and are not part of the generic 64-bit PowerPC chip architecture.

Register Name              Number        Abbreviation

General Register 0-31      0-31          r0-r31

Floating Register 0-31     32-63         f0-f31

Condition Register         64            CR

Floating-Point Status and  65            FPSCR
Control Register

* MQ Register              100           MQ or SPR0

Fixed-Point Exception      101           XER or SPR1
Register

* Real Time Clock          104           RTCU or SPR4
Upper Register

* Real Time Clock          105           RTCL or SPR5
Lower Register

Link Register              108           LR or SPR8

Count Register             109           CTR or SPR9

For kernel debuggers, the mapping for all privileged registers is also defined in this table.

Register Name              Number        Abbreviation

Machine State Register     66            MSR

Segment Register 0-15      70-85         SR0-SR15

Data Storage Interrupt     118           DSISR or SPR18
Status Register

Data Address Register      119           DAR or SPR19

Decrementer                122           DEC or SPR22

Storage Description        125           SDR1 or SPR25
Register 1

Machine Status             126           SRR0 or SPR26
Save/Restore Register 0

Machine Status             127           SRR1 or  SPR27
Save/Restore Register 1

Software-use Special       372           SPRG0 or SPR272
Purpose Register 0

Software-use Special       373           SPRG1 or SPR273
Purpose Register 1

Software-use Special       374           SPRG2 or SPR274
Purpose Register 2

Software-use Special       375           SPRG3 or SPR275
Purpose Register 3

Address Space Register     380           ASR or SPR280

External Access Register   382           EAR or SPR282

Time Base                  384           TB or SPR284

Time Base Upper            385           TBU or SPR285

Processor Version Register 387           PVR or SPR287

Instruction BAT Register   628           IBAT0U or SPR528
0 Upper

Instruction BAT Register   629           IBAT0L or SPR529
0 Lower

Instruction BAT Register   630           IBAT1U or SPR530
1 Upper

Instruction BAT Register   631           IBAT1L or SPR531
1 Lower

Instruction BAT Register   632           IBAT2U or SPR532
2 Upper

Instruction BAT Register   633           IBAT2L or SPR533
2 Lower

Instruction BAT Register   634           IBAT3U or SPR534
3 Upper

Instruction BAT Register   635           IBAT3L or SPR535
3 Lower

Data BAT Register 0 Upper  636           DBAT0U or SPR536

Data BAT Register 0 Lower  637           DBAT0L or SPR537

Data BAT Register 1 Upper  638           DBAT1U or SPR538

Data BAT Register 1 Lower  639           DBAT1L or SPR539

Data BAT Register 2 Upper  640           DBAT2U or SPR540

Data BAT Register 2 Lower  641           DBAT2L or SPR541

Data BAT Register 3 Upper  642           DBAT3U or SPR542

Data BAT Register 3 Lower  643           DBAT3L or SPR543

* Hardware Implementation  1108          HID0 or SPR1008
Register 0

* Hardware Implementation  1109          HID1 or SPR1009
Register 1

* Hardware Implementation  1110          HID2 or IABR or SPR1010
Register 2

* Hardware Implementation  1113          HID5 or DABR or SPR1013
Register 5

* Hardware Implementation  1123          HID15 or PIR or SPR1023
Register 15

The 64-bit PowerPC processor family defines the address class codes described in the following table:

Code                       Value         Meaning

ADDR_none                  0             No class specified