Machine Interface
Processor Architecture
The PowerPC Architecture: A Specification for A New Family of RISC Processors
defines the 64-bit PowerPC Architecture. Programs intended to execute directly on the
processor use the 64-bit PowerPC instruction set, and the instruction encodings and semantics of the
architecture.
An application program can assume that all instructions defined by the architecture that are neither
privileged nor optional exist and work as documented. However, the "Fixed-Point Move Assist"
instructions are not available in little-endian implementations. In little-endian mode, these instructions
always cause alignment exceptions in the 64-bit PowerPC Architecture; in big-endian mode they are
usually slower than a sequence of other instructions that have the same effect.
To be ABI-conforming, the processor must implement the instructions of the architecture, perform the
specified operations, and produce the expected results. The ABI neither places performance constraints
on systems nor specifies what instructions must be implemented in hardware. A software emulation of the
architecture could conform to the ABI.
Some processors might support the optional instructions in the 64-bit PowerPC Architecture, or
additional non-64-bit-PowerPC instructions or capabilities. Programs that use those instructions or
capabilities do not conform to the 64-bit PowerPC ABI; executing them on machines without the additional
capabilities gives undefined behavior.
Byte Ordering
The architecture defines an 8-bit byte, a 16-bit halfword, a 32-bit word, a 64-bit doubleword, and a
128-bit quadword. Byte ordering defines how the bytes that make up halfwords, words, doublewords, and
quadwords are ordered in memory. Most significant byte (MSB) byte ordering, or "big-endian" as it is
sometimes called, means that the most significant byte is located in the lowest addressed byte position
in a storage unit (byte 0). Least significant byte (LSB) byte ordering, or "little-endian" as it is sometimes
called, means that the least significant byte is located in the lowest addressed byte position in a storage
unit (byte 0).
The 64-bit PowerPC processor family supports either big-endian or little-endian byte ordering. This
specification defines two ABIs, one for each type of byte ordering. An implementation must state which
type of byte ordering it supports. The following figures illustrate the conventions for bit and byte numbering
within various width storage units. These conventions apply to both integer data and floating-point data,
where the most significant byte of a floating-point value holds the sign and at least the start of the exponent.
The figures show little-endian byte numbers in the upper right corners, big-endian byte numbers in the
upper left corners, and bit numbers in the lower corners.
 | Note |
---|
| In the 64-bit PowerPC Architecture documentation, the bits in a word are
numbered from left to right (MSB to LSB), and figures usually show only the big-endian
byte order. |
Fundamental Types
The following table shows how ANSI C scalar types correspond to those of the 64-bit PowerPC
processor. For all types, a NULL pointer has the value zero. The alignment column specifies the required
alignment of a field of the given type within a struct. The required alignment of a double or long double
field is word, not doubleword or quadword as might be expected from the size of the field. Variables may
be more strictly aligned than is shown in the table, but fields in a struct must follow the alignment
specified in order to ensure consistent struct mapping.
"Extended precision" is the IBM AIXTM 128-bit long double
format composed of two double-precision numbers with different magnitudes that do not overlap. The
high-order double-precision value (the one that comes first in storage) must have the larger magnitude. The value of the extended-precision number is the sum of the two double-precision values. For a value of
NaN or infinity, you must encode one of these values within the high-order double-precision value. The
low-order value is not significant. Extended precision provides the same range of double precision (about
10(-308) to 10308) but more precision (a variable amount, about 31 decimal digits or more). The
software support is restricted to round-to-nearest mode. Programs that use extended precision must ensure
that this rounding mode is in effect when extended-precision calculations are performed.
Type ANSI C sizeof Alignment PowerPC
-------------------------------------------------------------------------
Character char 1 byte unsigned byte
unsigned char
------------------------------------------------------------
signed char 1 byte signed byte
------------------------------------------------------------
short 2 halfword signed halfword
signed short
------------------------------------------------------------
unsigned short 2 halfword unsigned halfword
-------------------------------------------------------------------------
Integral int 4 word signed word
signed int
enum
------------------------------------------------------------
unsigned int 4 word unsigned word
------------------------------------------------------------
long int 8 doubleword signed doubleword
signed long
long long
------------------------------------------------------------
unsigned long 8 doubleword unsigned doubleword
unsigned long long
-------------------------------------------------------------------------
Pointer any * 8 doubleword unsigned doubleword
any (*) ()
-------------------------------------------------------------------------
Floating float 4 word single precision
------------------------------------------------------------
double 8 word double precision
------------------------------------------------------------
long double 16 word extended precision
|
 | Note |
---|
| When compared to the 32-bit PowerPC Processor Supplement, the size and alignment of
long has changed, and the alignment of double and long double has changed. A compiler may
provide options to use different sizes and alignments; however, any object compiled with those
options will not conform to the 64-bit PowerPC Processor Supplement. |
Aggregates and Unions
Aggregates (structures and arrays) and unions assume the alignment of their most strictly aligned
component, that is, the component with the largest alignment. The size of any object, including aggregates
and unions, is always a multiple of the alignment of the object. An array uses the same alignment as its
elements. Structure and union objects may require padding to meet size and alignment constraints:
An entire structure or union object is aligned on the same
boundary as its most strictly aligned member.
Each member is assigned to the lowest available offset with the appropriate
alignment. This may require internal padding, depending on the previous member.
If necessary, a structure's size is increased to make it a multiple of the
structure's alignment. This may require tail padding, depending on the last member.
In the following examples, members' byte offsets for little-endian implementations appear in the upper
right corners; offsets for big-endian implementations in the upper left corners.
Bit-fields
C struct and union definitions may have "bit-fields," defining integral objects with a specified
number of bits.
In the following table, a signed range goes from - (2(w - 1)) to
(2(w - 1)) - 1 and an unsigned range goes from 0 to
(2w) - 1.
Bit-field type Width (w) Range
-------------------------------------------------
signed char 1 to 8 signed
char unsigned
unsigned char unsigned
-------------------------------------------------
signed short 1 to 16 signed
short signed
unsigned short unsigned
-------------------------------------------------
signed int 1 to 32 signed
int signed
unsigned int unsigned
enum unsigned
-------------------------------------------------
signed long 1 to 64 signed
long signed
unsigned long unsigned |
"Plain" bit-fields (that is, those neither signed nor unsigned) may have either positive or negative
values, except in the case of plain char, which is always positive. Bit-fields obey the same size and
alignment rules as other structure and union members, with the following additions:
Bit-fields are allocated from right to left (least to most significant) on
little-endian implementations and from left to right (most to least significant) on
big-endian implementations.
Bit-fields are limited to at most 64 bits. Adjacent bit-fields that cross a
64-bit boundary will start a new storage unit.
The alignment of a bit-field is the same as the alignment of the base
type of the bit-field. Thus, an int bit-field will have word alignment.
Bit-fields must share a storage unit with other structure and union
members (either bit-field or non-bit-field) if and only if there is sufficient space within the
storage unit.
Unnamed bit-fields' types do not affect the alignment of a structure or
union, although an individual bit-field's member offsets obey the alignment constraints.
An unnamed, zero-width bit-field shall prevent any further member, bit-field or other,
from residing in the storage unit corresponding to the type of the zero-width bit-field.
 | Note |
---|
| The 64-bit PowerOpen ABI restricts bit-fields to be of type signed int, unsigned int, plain
int, long, or unsigned long. This document does not have that restriction. The 32-bit PowerPC Processor Supplement specifies that a bit-field must entirely reside in
a storage unit appropriate for its declared type. This document only restricts bit-fields to a 64-bit
storage unit. |
The following examples show struct and union members' byte offsets in the upper right corners for
little-endian implementations, and in the upper left corners for big-endian implementations. Bit numbers
appear in the lower corners.
 | Note |
---|
| In this example, the presence of the unnamed int and short fields does not affect the
alignment of the structure. They align the named members relative to the beginning of the
structure, but the named members may not be aligned in memory on suitable boundaries. For
example, the d members in an array of these structures will not all be on an int (4-byte) boundary.
|