64-bit PowerPC ELF Application Binary Interface Supplement 1.7 | ||
---|---|---|
<<< Previous | Next >>> |
The PowerPC Architecture: A Specification for A New Family of RISC Processors defines the 64-bit PowerPC Architecture. Programs intended to execute directly on the processor use the 64-bit PowerPC instruction set, and the instruction encodings and semantics of the architecture.
An application program can assume that all instructions defined by the architecture that are neither privileged nor optional exist and work as documented. However, the "Fixed-Point Move Assist" instructions are not available in little-endian implementations. In little-endian mode, these instructions always cause alignment exceptions in the 64-bit PowerPC Architecture; in big-endian mode they are usually slower than a sequence of other instructions that have the same effect.
To be ABI-conforming, the processor must implement the instructions of the architecture, perform the specified operations, and produce the expected results. The ABI neither places performance constraints on systems nor specifies what instructions must be implemented in hardware. A software emulation of the architecture could conform to the ABI.
Some processors might support the optional instructions in the 64-bit PowerPC Architecture, or additional non-64-bit-PowerPC instructions or capabilities. Programs that use those instructions or capabilities do not conform to the 64-bit PowerPC ABI; executing them on machines without the additional capabilities gives undefined behavior.
The architecture defines an 8-bit byte, a 16-bit halfword, a 32-bit word, a 64-bit doubleword, and a 128-bit quadword. Byte ordering defines how the bytes that make up halfwords, words, doublewords, and quadwords are ordered in memory. Most significant byte (MSB) byte ordering, or "big-endian" as it is sometimes called, means that the most significant byte is located in the lowest addressed byte position in a storage unit (byte 0). Least significant byte (LSB) byte ordering, or "little-endian" as it is sometimes called, means that the least significant byte is located in the lowest addressed byte position in a storage unit (byte 0).
The 64-bit PowerPC processor family supports either big-endian or little-endian byte ordering. This specification defines two ABIs, one for each type of byte ordering. An implementation must state which type of byte ordering it supports. The following figures illustrate the conventions for bit and byte numbering within various width storage units. These conventions apply to both integer data and floating-point data, where the most significant byte of a floating-point value holds the sign and at least the start of the exponent. The figures show little-endian byte numbers in the upper right corners, big-endian byte numbers in the upper left corners, and bit numbers in the lower corners.
![]() | Note |
---|---|
In the 64-bit PowerPC Architecture documentation, the bits in a word are numbered from left to right (MSB to LSB), and figures usually show only the big-endian byte order. |
+-------+-------+ |0 1|1 0| | msb | lsb | |0 7| 8 15| +-------+-------+ |
Figure 1. Bit and Byte Numbering in Halfwords
+-------+-------+-------+-------+ |0 3|1 2|2 1|3 0| | msb | | | lsb | |0 7|8 15|16 23|24 31| +-------+-------+-------+-------+ |
Figure 2. Bit and Byte Numbering in Words
+-------+-------+-------+-------+ |0 7|1 6|2 5|3 4| | msb | | | | |0 7|8 15|16 23|24 31| +-------+-------+-------+-------+ |4 3|5 2|6 1|7 0| | | | | lsb | |32 39|40 47|48 55|56 63| +-------+-------+-------+-------+ |
Figure 3. Bit and Byte Numbering in Doublewords
+-------+-------+-------+-------+ |0 15|1 14|2 13|3 12| | msb | | | | |0 7|8 15|16 23|24 31| +-------+-------+-------+-------+ |4 11|5 10|6 9|7 8| | | | | | |32 39|40 47|48 55|56 63| +-------+-------+-------+-------+ |8 7|9 6|10 5|11 4| | | | | | |64 71|72 79|80 87|88 95| +-------+-------+-------+-------+ |12 3|13 2|14 1|15 0| | | | | lsb | |96 103|104 111|112 119|120 127| +-------+-------+-------+-------+ |
Figure 4. Bit and Byte Numbering in Quadwords
The following table shows how ANSI C scalar types correspond to those of the 64-bit PowerPC processor. For all types, a NULL pointer has the value zero. The alignment column specifies the required alignment of a field of the given type within a struct. Variables may be more strictly aligned than is shown in the table, but fields in a struct must follow the alignment specified in order to ensure consistent struct mapping.
Type ANSI C sizeof Alignment PowerPC ------------------------------------------------------------------------- boolean _bool 1 byte unsigned byte ------------------------------------------------------------------------- Character char 1 byte unsigned byte unsigned char ------------------------------------------------------------ signed char 1 byte signed byte ------------------------------------------------------------ short 2 halfword signed halfword signed short ------------------------------------------------------------ unsigned short 2 halfword unsigned halfword ------------------------------------------------------------------------- Integral int 4 word signed word signed int enum ------------------------------------------------------------ unsigned int 4 word unsigned word ------------------------------------------------------------ long int 8 doubleword signed doubleword signed long long long ------------------------------------------------------------ unsigned long 8 doubleword unsigned doubleword unsigned long long ------------------------------------------------------------ __int128_t 16 quadword signed quadword ------------------------------------------------------------ __uint128_t 16 quadword unsigned quadword ------------------------------------------------------------------------- Pointer any * 8 doubleword unsigned doubleword any (*) () ------------------------------------------------------------------------- Floating float 4 word single precision ------------------------------------------------------------ double 8 doubleword double precision ------------------------------------------------------------ long double 16 quadword extended precision ------------------------------------------------------------------------- vector 16*char 16 quadword vector of signed bytes ------------------------------------------------------------ 16*unsigned 16 quadword vector of unsigned char bytes ------------------------------------------------------------ 8*short 16 quadword vector of signed halfwords ------------------------------------------------------------ 8*unsigned 16 quadword vector of unsigned short halfwords ------------------------------------------------------------ 4*int 16 quadword vector of signed words ------------------------------------------------------------ 4*unsigned int 16 quadword vector of unsigned words ------------------------------------------------------------ 4*float 16 quadword vector of floats |
"Extended precision" is the IBM AIXTM 128-bit long double format composed of two double-precision numbers with different magnitudes that do not overlap. The high-order double-precision value (the one that comes first in storage) must have the larger magnitude. The value of the extended-precision number is the sum of the two double-precision values.
Extended precision provides the same range of double precision (about 10**(-308) to 10**308) but more precision (a variable amount, about 31 decimal digits or more).
As the absolute value of the magnitude decreases (near the denormal range), the precision available in the low-order double also decreases.
When the value represented is in the denormal range, this representation provides no more precision than 64-bit (double) floating point.
The actual number of bits of percision can vary. If the low-order part is much less then 1 ULP of the high-order part, significant bits (either all 0's or all 1's) are implied between the significands of high-order and low-order numbers. Some algorithms that rely on having a fixed number of bits in the significand can fail when using "Extended precision".
This "Extended precision" differs from the IEEE 754 Standard in the following ways:
The software support is restricted to round-to-nearest mode. Programs that use extended precision must ensure that this rounding mode is in effect when extended-precision calculations are performed.
Does not fully support the IEEE special numbers NaN and INF. These values are encoded in the high-order double value only. The low-order value is not significant.
Does not support the IEEE status flags for overflow, underflow, and other conditions. These flag have no meaning in this format.
Aggregates (structures and arrays) and unions assume the alignment of their most strictly aligned component, that is, the component with the largest alignment. The size of any object, including aggregates and unions, is always a multiple of the alignment of the object. An array uses the same alignment as its elements. Structure and union objects may require padding to meet size and alignment constraints:
An entire structure or union object is aligned on the same boundary as its most strictly aligned member.
Each member is assigned to the lowest available offset with the appropriate alignment. This may require internal padding, depending on the previous member.
If necessary, a structure's size is increased to make it a multiple of the structure's alignment. This may require tail padding, depending on the last member.
In the following examples, members' byte offsets for little-endian implementations appear in the upper right corners; offsets for big-endian implementations in the upper left corners.
struct { char c; }; |
byte aligned, sizeof is 1 |
+-------+ |0 0| | c | +-------+ |
Figure 5. Structure Smaller Than a Word
struct { char c; char d; short s; int n; }; |
word aligned, sizeof is 8 |
little endian: +-------+-------+-------+-------+ | 2| 1| 0| | s | d | c | +-------+-------+-------+-------+ | 4| | n | +-------+-------+-------+-------+ big endian: +-------+-------+-------+-------+ |0 |1 |2 | | c | d | s | +-------+-------+-------+-------+ |4 | | n | +-------+-------+-------+-------+ |
Figure 6. No Padding
struct { char c; short s; }; |
halfword aligned, sizeof is 4 |
little endian: +-------+-------+-------+-------+ | 2| 1| 0| | s | pad | c | +-------+-------+-------+-------+ big endian: +-------+-------+-------+-------+ |0 |1 |2 | | c | pad | s | +-------+-------+-------+-------+ |
Figure 7. Internal Padding
struct { char c; double d; short s; }; |
doubleword aligned, sizeof is 24 |
little endian: +-------+-------+-------+-------+ | 1| 0| | pad | c | +-------+-------+-------+-------+ | 4| | pad | +-------+-------+-------+-------+ | 8| | d | +-------+-------+-------+-------+ | 12| | d | +-------+-------+-------+-------+ | 18| 16| | pad | s | +-------+-------+-------+-------+ | 20| | pad | +-------+-------+-------+-------+ big endian: +-------+-------+-------+-------+ |0 |1 | | c | pad | +-------+-------+-------+-------+ |4 | | pad | +-------+-------+-------+-------+ |8 | | d | +-------+-------+-------+-------+ |12 | | d | +-------+-------+-------+-------+ |16 |18 | | s | pad | +-------+-------+-------+-------+ |20 | | pad | +-------+-------+-------+-------+ |
Figure 8. Internal and Tail Padding
union { char c; short s; int j; }; |
word aligned, sizeof is 4 |
little endian: +-------+-------+-------+-------+ | 1| 0| | pad | c | +-------+-------+-------+-------+ | 2| 0| | pad | s | +-------+-------+-------+-------+ | 0| | j | +-------+-------+-------+-------+ big endian: +-------+-------+-------+-------+ |0 |1 | | c | pad | +-------+-------+-------+-------+ |0 |2 | | s | pad | +-------+-------+-------+-------+ |0 | | j | +-------+-------+-------+-------+ |
Figure 9. Union Allocation
C struct and union definitions may have "bit-fields," defining integral objects with a specified number of bits.
In the following table, a signed range goes from - (2(w - 1)) to (2(w - 1)) - 1 and an unsigned range goes from 0 to (2w) - 1.
Bit-field type Width (w) Range ------------------------------------------------- signed char 1 to 8 signed char unsigned unsigned char unsigned ------------------------------------------------- signed short 1 to 16 signed short signed unsigned short unsigned ------------------------------------------------- signed int 1 to 32 signed int signed unsigned int unsigned enum unsigned ------------------------------------------------- signed long 1 to 64 signed long signed unsigned long unsigned |
"Plain" bit-fields (that is, those neither signed nor unsigned) may have either positive or negative values, except in the case of plain char, which is always positive. Bit-fields obey the same size and alignment rules as other structure and union members, with the following additions:
Bit-fields are allocated from right to left (least to most significant) on little-endian implementations and from left to right (most to least significant) on big-endian implementations.
Bit-fields are limited to at most 64 bits. Adjacent bit-fields that cross a 64-bit boundary will start a new storage unit.
The alignment of a bit-field is the same as the alignment of the base type of the bit-field. Thus, an int bit-field will have word alignment.
Bit-fields must share a storage unit with other structure and union members (either bit-field or non-bit-field) if and only if there is sufficient space within the storage unit.
Unnamed bit-fields' types do not affect the alignment of a structure or union, although an individual bit-field's member offsets obey the alignment constraints. An unnamed, zero-width bit-field shall prevent any further member, bit-field or other, from residing in the storage unit corresponding to the type of the zero-width bit-field.
![]() | Note |
---|---|
The 64-bit PowerOpen ABI restricts bit-fields to be of type signed int, unsigned int, plain int, long, or unsigned long. This document does not have that restriction. The 32-bit PowerPC Processor Supplement specifies that a bit-field must entirely reside in a storage unit appropriate for its declared type. This document only restricts bit-fields to a 64-bit storage unit. |
The following examples show struct and union members' byte offsets in the upper right corners for little-endian implementations, and in the upper left corners for big-endian implementations. Bit numbers appear in the lower corners.
0x01020304 +-------+-------+-------+-------+ |0 3|1 2|2 1|3 0| | 01 | 02 | 03 | 04 | |0 7|8 15|16 23|24 31| +-------+-------+-------+-------+ |
Figure 10. Bit Numbering
struct { int j : 5; int k : 6; int m : 7; }; |
word aligned, sizeof is 4 |
little endian: +----------+-------+------+-----+ | | | | 0| | pad | m | k | j | |0 13|14 20|21 26|27 31| +----------+-------+------+-----+ big endian: +-----+------+-------+----------+ |0 | | | | | j | k | m | pad | |0 4|5 10|11 17|18 31| +-----+------+-------+----------+ |
Figure 11. Bit-field Allocation
struct { short s : 9; int j : 9; char c; short t : 9; short u : 9; char d; }; |
word aligned, sizeof is 8 |
little endian: +-------+-----+--------+--------+ | 3| | | 0| | c | pad | j | s | |0 7|8 13|14 22|23 31| +-------+-----+--------+--------+ | 7| | | 4| | d | pad | u | t | |0 7|8 13|14 22|23 31| +-------+-----+--------+--------+ big endian: +--------+--------+-----+-------+ |0 | | |3 | | s | j | pad | c | |0 8|9 17|18 23|24 31| +--------+--------+-----+-------+ |4 | | |7 | | t | u | pad | d | |0 8|9 17|18 23|24 31| +--------+--------+-----+-------+ |
Figure 12. Boundary Alignment
struct { long i : 56; int j : 9: }; |
doubleword aligned, sizeof is 16 |
little endian: +-------------------------------+ | 0| | i | |0 31| +-------+-----------------------+ | | 4| | pad | i | |32 39|40 63| +-------+--------------+--------+ | | 8| | pad | j | |0 22|23 31| +----------------------+--------+ | 12| | pad | |0 31| +-------------------------------+ big endian: +-------------------------------+ |0 | | i | |0 31| +-----------------------+-------+ |4 | | | i | pad | |32 55|56 63| +--------+--------------+-------+ |8 | | | j | pad | |0 8|9 31| +----------------------+--------+ |12 | | pad | |0 31| +-------------------------------+ |
Figure 13. Doubleword Boundary Alignment
struct { char c; short s : 8; }; |
halfword aligned, sizeof is 2 |
little endian: +-------+-------+ | 1| 0| | s | c | |0 7|8 15| +-------+-------+ big endian: +-------+-------+ |0 |1 | | c | s | |0 7|8 15| +-------+-------+ |
Figure 14. Storage Unit Sharing
union { char c; short s : 8; }; |
halfword aligned, sizeof is 2 |
little endian: +-------+-------+ | 1| 0| | pad | c | |0 7|8 15| +-------+-------+ | 1| 0| | pad | s | |0 7|8 15| +-------+-------+ big endian: +-------+-------+ |0 |1 | | c | pad | |0 7|8 15| +-------+-------+ |0 |1 | | s | pad | |0 7|8 15| +-------+-------+ |
Figure 15. Union Allocation
struct { char c; int : 0; char d; short : 9; char e; }; |
byte aligned, sizeof is 8 |
little endian: +-----------------------+-------+ | 1| 0| | :0 | c | |0 23|24 31| +-------+------+--------+-------+ | 7| | | 4| | e | pad | :9 | d | |0 7|8 14|15 23|24 31| +-------+------+--------+-------+ big endian: +-------+-----------------------+ |0 |1 | | c | :0 | |0 7|8 31| +-------+--------+------+-------+ |4 | | |7 | | d | :9 | pad | e | |0 7|8 16|17 23|24 31| +-------+--------+------+-------+ |
Figure 16. Unnamed bit-fields
![]() | Note |
---|---|
In this example, the presence of the unnamed int and short fields does not affect the alignment of the structure. They align the named members relative to the beginning of the structure, but the named members may not be aligned in memory on suitable boundaries. For example, the d members in an array of these structures will not all be on an int (4-byte) boundary. |
<<< Previous | Home | Next >>> |
Software Installation | Function Calling Sequence |